1. Field of the Invention
This invention relates to contactless testing of electronic activity in an integrated circuit chip-to-test after passivation thereof, and more particularly relates to a static or dynamic testing procedure by which instantaneous operational voltage at one or more test points of the integrated circuit is interrogated by a pulsed light source means so as to induce photoemission for result interpretation by means of capacitive voltage contrast.
2. Description of the Prior Art
To analyze manufacturing failure, when faults have been detected in the final functional tests performed on integrated circuit chips having a passivation layer thereon, the usual procedure is to single out complete chips with a view to locating the source of the malfunction. The chips of interest here always have a passivation layer thereon, since passivation is performed prior to the final functional tests. Tests performed on internal nodes of these chips should then be conducted without removing the passivation layer, for the removal of the passivation layer may also remove or alter the malfunction of the chip or it may even introduce new errors which prohibit the detection of genuine errors. Since the voltage at the tested internal nodes must be probed at the surface of the passivation layer, result interpretation by means of capacitive voltage contrast is mandatory for this purpose.
In the present state of the art, photon induced photoemission is not appropriate for testing passivated chips so as to obtain results by means of capacitive voltage contrast, due to the lack of pulsed light sources, e.g., pulsed laser systems, both having photon energies which exceed the work function of the passivation layer and having repetition rates in the MHz range. Passivation layers usually are made of polyimide, which has a work function of about 7 eV, or of aluminum oxide, which has a work function of about 8 eV. Existing pulsed light source means with such high photon energies are pulsed lasers having low repetition rates of a few kHz which do not allow to perform dynamic testing of electronic activity in the integrated circuit because it is extremely difficult to synchronize such low repetition rates with chip signals related to clock rates in the MHz range. To enable such testing with currently available picosecond lasers having pulse repetition rates of up to 1 GHz, the work function of the passivation layer should not exceed about 2 eV. However, no material suitable for making a passivation layer is known to have such a low work function.
Electron beam testing of passivated chips delivers results by means of an analysis of capacitive voltage contrast and the detection of voltage changes by this method is well established, but the probing of static voltages is hindered by charging of the passivation layer. Also, this technique is unsuitable for integrated circuits of small dimensions operated in the MHz range (Simon C. J. Garth, "Electron beam testing of ultra large scale integrated circuits", Microelectronic Engineering 4 (1986) 121-138, cf. in particular pp. 131-132).
The following publications are representative of the prior art and scientific background:
U.S. Pat. No. 4,644,264 discloses a method for contactless testing of electronic activity in an integrated circuit chip-to-test after passivation thereof. The chip-to-test has a number of circuits and input/output connections and a plurality of test points connected to the circuits. It is passivated by means of a passivation layer which is covered by an overlayer. It is placed and supported in mounting means provided with electrical connections complementary to the input/output connections of the chip-to-test. The test points of the chip-to-test can be accessed by laser photons from a pulsed laser means. When the circuits on the chip-to-test are exercised to cause electronic activity therein, this provides at the test points, a voltage related to the circuit exercise. However, in this technique, the overlayer is used to collect photoelectrons tunneling through the passivation layer. Thus, the overlayer has to be conductive and a special control of the thickness of the passivation layer is required to ensure tunneling. This precludes currently manufactured normally passivated chips from being tested by this technique.
U.S. Pat. No. 4,703,260 discloses a method derived from that disclosed by U.S. Pat. No. 4,644,264 in that it is performed in vacuum and there are provided electron detector means for detecting electrons which pass through the passivation layer and the metallic overlayer and are emitted into the vacuum. However, this method is not capable of capacitive voltage contrast analysis because the conductive nature of the overlayer results in a smearing out of the spatial voltage contrast.
U.S. Pat. No. 4,706,018 discloses the principle of capacitive voltage contrast analysis performed in vacuum by means of laser photon induced photoemission on an integrated circuit chip-to-test devoid of passivation layer. The method so disclosed is not applicable to passivated chip-to-test for reasons already stated above, i.e., currently there is known no laser system delivering both sufficient photon energies and sufficient repetition rates.